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AT/TSC8x251G2D
4135F–8051–11/06
Configuration Bytes
The TSC80251G2D derivatives provide user design flexibility by configuring certain
operating features at device reset. These features fall into the following categories:
external memory interface (Page mode, address bits, programmed wait states and
the address range for RD#, WR#, and PSEN#)
source mode/binary mode opcodes
selection of bytes stored on the stack by an interrupt
mapping of the upper portion of on-chip code memory to region 00:
Two user configuration bytes UCONFIG0 (see Table 11) and UCONFIG1 (see Table
12) provide the information.
When EA# is tied to a low level, the configuration bytes are fetched from the external
address space. The TSC80251G2D derivatives reserve the top eight bytes of the mem-
ory address space (FF:FFF8h-FF:FFFFh) for an external 8-byte configuration array.
Only two bytes are actually used: UCONFIG0 at FF:FFF8h and UCONFIG1 at
FF:FFF9h.
For the mask ROM devices, configuration information is stored in on-chip memory (see
ROM Verifying). When EA# is tied to a high level, the configuration information is
retrieved from the on-chip memory instead of the external address space and there is no
restriction in the usage of the external memory.
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